1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device which can implement formation of a capacitance element therein and miniaturization thereof, and a method of manufacturing the same.
2. Description of the Background Art
Conventionally, when a capacitance element is formed in an integrated circuit of a semiconductor device, a capacitance element formed of opposing interconnection layers serving as electrodes, and an MOS capacitor formed between the source/drain region and the gate of an MOS transistor are used.
There are capacitance elements ranging from a small one used for delaying a signal in an integrated circuit to a large one used as a decoupling capacitor which prevents generation of noise when the power supply voltage externally supplied at the time of operation of the integrated circuit is internally changed.
Referring to FIG. 31, description will be given of a configuration concept of a semiconductor memory device.
In the figure, a semiconductor substrate is divided into a memory cell array region 200, a peripheral circuit region 202, and an interconnection region 204.
A power supply decoupling capacitor requiring a large capacitance is conventionally formed under interconnection region 204 with an MOS capacitor.
This is because the large thickness of an insulating layer between interconnection layers causes a small capacitance per unit area in the case of a capacitance element formed of opposing interconnection layers. In addition, the interconnection layers used as a capacitance element cannot be used as a signal interconnection.
On the other hand, when a capacitance element is formed using an MOS capacitor, a capacitance is formed between the gate electrode opposing to a gate oxide film of an MOS transistor and a channel of the MOS transistor in an on state. Therefore, a relatively large capacitance per unit area can be obtained.
Referring to FIG. 32, description will be given of a configuration of a power supply decoupling capacitor formed using an MOS capacitor.
In the figure, an example of a power supply decoupling capacitor using an n channel MOS transistor is shown on the left, and an example of a power supply decoupling capacitor using a p channel MOS transistor is shown on the right.
The power supply decoupling capacitor using an n channel MOS transistor on the left includes a p well 208 formed on a p substrate 206. An n channel MOS transistor 210 is formed on the surface of p well 208. The source/drain region of n channel MOS transistor 210 is supplied with the ground potential (V.sub.SS).
The gate electrode of n channel MOS transistor 210 is supplied with the external power supply potential (V.sub.CC). p well 208 is supplied with an internally generated negative potential (V.sub.BB) through a p.sup.+ impurity region 212.
The power supply decoupling capacitor using a p channel MOS transistor includes an n well 207 formed on p substrate 206. A p channel MOS transistor 214 is formed on the surface of n well 207.
The source region and the drain region of p channel MOS transistor 214 are supplied with the external power supply potential (V.sub.CC). The gate electrode of p channel MOS transistor 214 is supplied with the ground potential (V.sub.SS). n well 207 is supplied with the external power supply potential (V.sub.CC) through an n.sup.+ impurity region 216.
In the power supply decoupling capacitor, the voltage applied to the source/drain region of the MOS transistor turns on the channel region of the MOS transistor, thereby forming a capacitor between the channel region and the gate electrode.
Although an MOS capacitor is generally used as a power supply decoupling capacitor, it can also be used for delaying a signal in a peripheral circuit. In this case, a signal node which is to be delayed has only to be connected to the gate electrode of the MOS capacitor.
Referring to FIG. 33, description will be given of a configuration of a dynamic type random access memory. FIG. 33 is a sectional concept diagram of a dynamic type random access memory (hereinafter referred to as a "DRAM") disclosed in a brochure of a seminar (SDM90-201-p43, 1990) of Institute of Electronics, Information and Communication Engineers of Japan.
The DRAM includes on p substrate 206 a peripheral circuit region 1000 including a p well 218 on which an n channel MOS transistor 226 is formed, a peripheral circuit region 2000 including an n well 220 on which a sense amplifier, for example, is formed by a p channel MOS transistor 228 or the like, and a storing circuit region 3000 including a p well 222 on which a memory cell or the like is formed by an n channel MOS transistor 232 or the like.
In peripheral circuit region 1000, the ground potential (V.sub.SS) is applied to p well 218 through a p.sup.+ impurity region 224.
In peripheral circuit region 2000, the external power supply potential (V.sub.CC) is applied to n well 220 through an n.sup.+ impurity region 230.
In storing circuit region 3000, the internally generated negative potential (V.sub.BB) is applied to p well 222 through a p.sup.+ impurity region 234.
n well 220 is formed so as to surround p well 222 for isolating p substrate 206 supplied with the same potential (V.sub.SS) as that of p well 218 and p well 222 supplied with the V.sub.BB potential.
The configuration in which n well 220 is formed under p well 222 as described above is generally called as a triple well configuration.
When a power supply decoupling capacitor is formed in such a DRAM having a triple well configuration, n channel MOS transistor 210 is provided beside p.sup.+ impurity region 224 in p well 218, for example, as shown in FIG. 34.
FIG. 35 is a sectional concept diagram of a DRAM disclosed in Proceedings (p249) of International Solid-State Circuits Conference held in 1989.
The DRAM in this figure includes on n substrate 206 a peripheral circuit region 4000 including an n well 236 on which a voltage dropping circuit, for example, is formed by a p channel MOS transistor 244 or the like, a peripheral circuit region 5000 including a p well region 238 on which an input protecting circuit, for example, is formed by an n channel MOS transistor 250 or the like, a peripheral circuit region 6000 including an n well 240 on which a sense amplifier, for example, is formed by a p channel MOS transistor 252 or the like, and a storing circuit region 7000 including a p well 242 on which a memory cell, for example, is formed by an n channel MOS transistor 260 or the like.
In peripheral circuit region 4000, the external power supply potential (V.sub.CC) is applied to n well 236 through an n.sup.+ impurity region 246.
In peripheral circuit region 5000, the ground potential (V.sub.SS) is applied to p well 238 through p.sup.+ impurity regions 248, 256.
In peripheral circuit region 6000, the internal power supply potential (V.sub.INT) is applied to n well 240 through an n.sup.+ impurity region 254.
In storing circuit region 7000, the internally generated negative potential (V.sub.BB) iS applied to p well 242 through a p.sup.+ impurity region 258.
The DRAM shown in this figure also has a triple well configuration in which p well 238 is formed so as to surround n well 240 for isolating n substrate 206 supplied with the same potential (V.sub.CC) as that of n well 236 and n well 240 supplied with the internal power supply potential (V.sub.INT).
As described above, the conventional triple well configuration is used for isolating wells of the same conductivity type having different potentials.
When a power supply decoupling capacitor is formed in the DRAM shown in FIG. 35, a p channel MOS transistor 214 is provided in a region of n well 236, for example, as shown in FIG. 36.
However, in the above conventional technique, when a decoupling capacitor is formed in the conventional DRAM configuration, the MOS transistor must be formed on the surface of the well region as shown in FIGS. 34 and 36.
As a result, the area of the semiconductor device is increased, preventing miniaturization of the semiconductor device.
When the decoupling capacitor is insufficiently connected to an element, noise cannot be eliminated, resulting in malfunction of the semiconductor device.